Intellectual Property
IMETAL OXIDE SEMICONDUCTOR-BASED LIGHT EMITTING DEVICE
Publication number: 20240339567
Abstract: The techniques described herein relate to an optoelectronic semiconductor light emitting device including a single crystal (AlxGa1-x)2O3 substrate including a monoclinic or corundum crystal symmetry, where 0<x<1, and an optical emission region including an epitaxial oxide layer disposed on the single crystal (AlxGa1-x)2O3 substrate. The optical emission region can be configured to emit light having a wavelength in a range from 150 nm to 425 nm. The techniques described herein also relate to a semiconductor structure including a single crystal (AlxGa1-x)2O3 substrate including a monoclinic or corundum crystal symmetry, where 0<x<1, and an epitaxial oxide layer disposed on the single crystal (AlxGa1-x)2O3 substrate. The epitaxial oxide layer can include a polar form of (AlyGa1-y)2O3 with a hexagonal crystal symmetry, where 0?y?1.
Type: Application
Filed: June 20, 2024
Publication date: October 10, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
Epitaxial oxide device with impact ionization
Patent number: 12095006
Abstract: The present disclosure describes epitaxial oxide devices with impact ionization. In some embodiments, a semiconductor device comprises: a first semiconductor layer; a second semiconductor layer coupled to the first semiconductor layer; and a first and a second electrical contact coupled to the second and first semiconductor layers, respectively. The first semiconductor layer can comprise a first epitaxial oxide material with a first bandgap and an impact ionization region. The second semiconductor layer can comprise a second epitaxial oxide material with a second bandgap that is wider than the first bandgap.
Type: Grant
Filed: May 23, 2022
Date of Patent: September 17, 2024
Assignee: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
Epitaxial oxide materials, structures, and devices
Patent number: 12087880
Abstract: The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, including: a substrate; a first epitaxial oxide layer comprising (Nix1Mgy1Zn1-x1-y1)(Alq1Ga1-q1)2O4 wherein 0?x1?1, 0?y1?1 and 0?q1?1; and a second epitaxial oxide layer comprising (Nix2Mgy2Zn1-x2-y2)(Alq2Ga1-q2)2O4 wherein 0?x2?1, 0?y2?1 and 0?q2?1. In some cases, at least one condition selected from x1?x2, y1?y2, and q1?q2 is satisfied.
Type: Grant
Filed: February 22, 2022
Date of Patent: September 10, 2024
Assignee: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
Patent number: 12074195
Abstract: In some embodiments, the techniques described herein relate to a multilayered semiconductor diode device including: a substrate including silicon carbide (SiC); an epitaxial transition layer including a first semiconductor oxide material or SiC, wherein the epitaxial transition layer is on the substrate; an epitaxial drift layer including a second semiconductor oxide material, wherein the epitaxial drift layer is on the epitaxial transition layer; and a metal layer above the epitaxial drift layer, wherein the metal layer and the epitaxial drift layer form a Schottky barrier junction. In some embodiments, a method of forming a multilayered semiconductor diode device includes: providing a substrate including silicon carbide (SiC); forming an epitaxial transition layer including a first semiconductor oxide material or SiC; forming an epitaxial drift layer including a second semiconductor oxide material; and forming a metal layer above the epitaxial drift layer forming a Schottky barrier junction.
Type: Grant
Filed: December 22, 2023
Date of Patent: August 27, 2024
Assignee: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
METHODS AND MATERIAL DEPOSITION SYSTEMS FOR FORMING SEMICONDUCTOR LAYERS
Publication number: 20240282574
Abstract: In embodiments, methods of configuring a molecular beam epitaxy system include providing a rotation mechanism configured to rotate a substrate deposition plane of a substrate around a center axis of the substrate deposition plane. A positioning mechanism is provided, being configured to allow the substrate deposition plane and an exit aperture of at least one material source in a plurality of material sources to be adjusted in position relative to each other between production runs. The at least one material source has a predetermined material ejection spatial distribution with a symmetry axis that intersects the substrate at a point offset from the center axis. A size of a reaction chamber, that houses the rotation mechanism and the plurality of material sources, is scaled based on the orthogonal distance and the lateral distance in relationship to a radius of the substrate.
Type: Application
Filed: April 13, 2024
Publication date: August 22, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
Publication number: 20240266469
Abstract: The techniques described herein relate to a transistor including a substrate including sapphire, an epitaxial channel layer on the substrate, and an epitaxial gate layer on the channel layer. The epitaxial channel layer can include ?-Ga2O3, with a first bandgap. The epitaxial gate layer can include an oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap. The transistor can also include electrical contacts, including: a source electrical contact coupled to the epitaxial channel layer; a drain electrical contact coupled to the epitaxial channel layer; and a gate electrical contact coupled to the epitaxial gate layer.
Type: Application
Filed: April 8, 2024
Publication date: August 8, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
BURIED CONTACT LAYER FOR UV EMITTING DEVICE
Publication number: 20240266464
Abstract: In some embodiments, a light emitting structure comprises a layered semiconductor stack comprising a first set of doped layers, a second layer, a light emitting layer positioned between the first set of doped layers and the second layer, and an electrical contact to the first set of doped layers. The first set of doped layers can comprise a first sub-layer and a second sub-layer, wherein the first or the second sub-layer is adjacent to the light emitting layer. The electrical contact can be coupled to the second sub-layer. The first and second sub-layers can be doped n-type, and an electrical conductivity of the second sub-layer can be higher than an electrical conductivity of the first sub-layer. The first sub-layer, the second sub-layer, and the light emitting layer can each comprise a superlattice.
Type: Application
Filed: April 3, 2024
Publication date: August 8, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventors: Johnny Cai Tang, Chun To Lee, Guilherme Tosi, Christopher Flynn, Liam Anderson, Timothy William Bray, Petar Atanackovic
MATERIAL DEPOSITION SYSTEM EQUIPMENT MAINTENANCE
Publication number: 20240254621
Abstract: A material deposition system comprises a growth chamber configured for a vacuum environment. A fluid circulation panel is inside the growth chamber, spaced apart from an inner surface of the growth chamber and comprising walls around an interior of the fluid circulation panel. An injector pipe is in the interior of the fluid circulation panel and may include a plurality of holes along a length of the injector pipe. A first port may be in communication with the interior of the fluid circulation panel, where the injector pipe is inserted through the first port. A gas heater is configured to supply a heated gas into the interior of the fluid circulation panel to heat the walls of the fluid circulation panel and thereby heat the inner surface of the growth chamber.
Type: Application
Filed: March 13, 2024
Publication date: August 1, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
Publication number: 20240258460
Abstract: The techniques described herein relate to a transistor, including a substrate, an epitaxial buffer layer, an epitaxial channel layer, and a gate layer. The substrate includes a first oxide material with a first crystal symmetry, the epitaxial buffer layer includes a second oxide material with a second crystal symmetry, the epitaxial channel layer includes a third oxide material with a third crystal symmetry and a first bandgap, and the gate layer includes a fourth oxide material with a second bandgap. The first crystal symmetry is different from either the second crystal symmetry or the third crystal symmetry, and the second bandgap is wider than the first bandgap. The transistor also includes electrical contacts including a source electrical contact coupled to the epitaxial channel layer, a drain electrical contact coupled to the epitaxial channel layer, and a gate electrical contact coupled to the gate layer.
Type: Application
Filed: April 8, 2024
Publication date: August 1, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
Publication number: 20240170612
Abstract: In some embodiments, the techniques described herein relate to an epitaxial oxide transistor. The transistor can include: a substrate; a channel layer including a first epitaxial semiconductor layer on the substrate; a gate layer including a second epitaxial semiconductor layer on the first epitaxial semiconductor layer; a source electrode and a drain electrode coupled to the channel layer; and a gate electrode coupled to the gate layer. The first epitaxial semiconductor layer can include a first polar oxide material and the second epitaxial semiconductor layer can include a second polar oxide material. The first polar oxide material and the second polar oxide material can include cation-polar surfaces oriented towards or away from the substrate, and the second polar oxide material can include a wider bandgap than the first polar oxide material.
Type: Application
Filed: January 26, 2024
Publication date: May 23, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
Optoelectronic device including a superlattice
Patent number: 11990338
Abstract: In embodiments, an optoelectronic device comprises a substrate formed of magnesium oxide, and a multi-region stack epitaxially deposited upon the substrate. The multi-region stack may comprise a non-polar crystalline material structure along a growth direction, or may comprise a crystal polarity having an oxygen-polar crystal structure or a metal-polar crystal structure along the growth direction. In some cases, at least one region of the multi-region stack is a bulk semiconductor material comprising Mg(x)Zn(1-x)O. In some cases, at least one region of the multi-region stack is a superlattice comprising MgO and Mg(x)Zn(1-x)O.
Type: Grant
Filed: February 9, 2023
Date of Patent: May 21, 2024
Assignee: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
MATERIAL DEPOSITION SYSTEM EQUIPMENT MAINTENANCE
Publication number: 20240158912
Abstract: Methods and systems for material deposition system equipment maintenance include evacuating a growth chamber of a material deposition system. The system comprises a growth chamber configured for a vacuum environment. A fluid circulation panel is inside the growth chamber, spaced apart from an inner surface of the growth chamber and comprising walls around an interior of the fluid circulation panel. A first port is in communication with the interior of the fluid circulation panel. A gas heater is coupled to the first port to heat and supply a heated gas into the interior of the fluid circulation panel to heat the walls of the fluid circulation panel. Methods include heating the gas with the gas heater and supplying the gas into the interior of the fluid circulation panel. The fluid circulation panel is heated, using the gas supplied to the interior of the fluid circulation panel.
Type: Application
Filed: November 16, 2022
Publication date: May 16, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
Buried contact layer for UV emitting device
Patent number: 11978824
Abstract: In some embodiments, a light emitting structure comprises a layered semiconductor stack comprising a first set of doped layers, a second layer, a light emitting layer positioned between the first set of doped layers and the second layer, and an electrical contact to the first set of doped layers. The first set of doped layers can comprise a first sub-layer, a second sub-layer, and a third sub-layer, wherein the third sub-layer is adjacent to the light emitting layer. The electrical contact can be coupled to the second sub-layer. The first, second and third sub-layers can be doped n-type, and an electrical conductivity of the second sub-layer can be higher than an electrical conductivity of the first and third sub-layers. The first, second and third sub-layers, the light emitting layer, and the second layer can each comprise a superlattice.
Type: Grant
Filed: March 21, 2023
Date of Patent: May 7, 2024
Assignee: Silanna UV Technologies Pte Ltd
Inventors: Johnny Cai Tang, Chun To Lee, Guilherme Tosi, Christopher Flynn, Liam Anderson, Timothy William Bray, Petar Atanackovic
SURFACE CHARACTERIZATION OF MATERIALS USING CATHODOLUMINESCENCE
Publication number: 20240125718
Abstract: Methods and systems include generating, from an electron beam generator, an electron beam in a vacuum chamber. A mounting platform in the vacuum chamber is configured to support a material. The electron beam is directed at a surface region of the material at a grazing angle. A detector assembly, which may have an optical entry path positioned above the surface region, receives cathodoluminescent light emission arising from the electron beam transferring energy to the surface region. The detector assembly determines spectral characteristics of the cathodoluminescent light emission to characterize the surface region.
Type: Application
Filed: September 29, 2023
Publication date: April 18, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventors: Petar Atanackovic, Dominic Lane
ULTRAWIDE BANDGAP SEMICONDUCTOR DEVICES INCLUDING MAGNESIUM GERMANIUM OXIDES
Publication number: 20240096970
Abstract: Various forms of MgxGe1-xO2-x are disclosed, where the MgxGe1-xO2-x are epitaxial layers formed on a substrate comprising a substantially single crystal substrate material. The epitaxial layer of MgxGe1-xO2-x has a crystal symmetry compatible with the substrate material. Semiconductor structures and devices comprising the epitaxial layer of MgxGe1-xO2-x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices. Also disclosed is single crystal MgxGe1-xO2-x, with x having a value of 0?x<1. The single crystal MgxGe1-xO2-x may comprise a dopant chosen from Ga, Al, Li+, N3+. The single crystal MgxGe1-xO2-x may comprise a p-type conductivity.
Type: Application
Filed: October 30, 2023
Publication date: March 21, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
SEMICONDUCTOR STRUCTURE WITH SUPERLATTICES
Publication number: 20240097066
Abstract: In some embodiments, a semiconductor structure includes a first conductivity type region comprising a first superlattice, and an i-type active region adjacent to the first conductivity type region comprising an i-type superlattice. The first conductivity type region can be a p-type region or an n-type region. The first superlattice can be comprised of a plurality of first unit cells comprising a first set of single crystal layers, and the i-type superlattice can be comprised of a plurality of i-type unit cells comprising a second set of single crystal layers. An average alloy content of the plurality of the first unit cells and the i-type unit cells can be constant along a growth direction. The structure can be configured such that electrons and holes recombine to generate a spectrum of light with a longest wavelength peak that corresponds to a transition between electron and hole confined energy states within the i-type superlattice.
Type: Application
Filed: November 29, 2023
Publication date: March 21, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
EPITAXIAL OXIDE MATERIALS, STRUCTURES, AND DEVICES
Publication number: 20240072205
Abstract: The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, the techniques described herein relate to a transistor, including: a substrate including a first oxide material; an epitaxial oxide layer on the substrate including a second oxide material with a first bandgap; a gate layer on the epitaxial oxide layer, the gate layer including a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The second oxide material can include: one or two of Li, Ni, Al, Ga, Mg, and Zn; Ge; and O. The second oxide can also include (NixMgyZn1-x-y)2GeO4 wherein 0?x?1 and 0?y?1. The electrical contacts can include: a source electrical contact coupled to the epitaxial oxide layer; a drain electrical contact coupled to the epitaxial oxide layer; and a first gate electrical contact coupled to the gate layer.
Type: Application
Filed: October 3, 2023
Publication date: February 29, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
OXIDE COMPOSITIONS AND METHODS OF DEPOSITING EPITAXIAL LAYERS
Publication number: 20240072206
Abstract: In some embodiments, a composition of matter includes Li and F atoms within a single crystal Ga2O3 host including a monoclinic, orthorhombic, cubic, corundum, or hexagonal crystal symmetry, or within a single crystal LiGaO2 host including an orthorhombic or trigonal crystal symmetry. In some embodiments, a method includes sublimating a lithium fluoride (LiF) bulk crystal within a Knudsen cell to provide both Li and F and co-depositing the Li and F with an elemental Ga beam under an activated oxygen environment. The method can further include growing, on a growth surface of a substrate, an epitaxial layer including the Li, the F, the Ga, and the activated oxygen within an epitaxially formed Ga2O3 or LiGaO2 host.
Type: Application
Filed: November 1, 2023
Publication date: February 29, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
OXIDE SEMICONDUCTOR STRUCTURES AND DEVICES
Publication number: 20240072207
Abstract: In some embodiments, an optoelectronic semiconductor light emitting device includes a single crystal LiF substrate and an optical emission region including an epitaxial oxide layer disposed on the substrate. The optical emission region can be configured to emit light having a wavelength in a range from 150 nm to 425 nm. In some embodiments, a semiconductor structure includes a single crystal LiF substrate and an epitaxial oxide layer disposed on the substrate, where the epitaxial layer includes MgxAl2(1?x)O3?2x or MgxGa2(1?x)O3?2x where 0?x?1, or a polar form of Ga2O3 with a hexagonal crystal symmetry.
Type: Application
Filed: November 1, 2023
Publication date: February 29, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic
ULTRAWIDE BANDGAP SEMICONDUCTOR DEVICES INCLUDING MAGNESIUM GERMANIUM OXIDES
Publication number: 20240063271
Abstract: Various forms of MgxGe1?xO2?x are disclosed, where an epitaxial layer comprises single crystal MgxGe1?xO2?x, with x having a value of 0?x<1, wherein the single crystal MgxGe1?xO2?x has a crystal symmetry compatible with a substrate or with an underlying layer on which the single crystal MgxGe1?xO2?x is grown. Semiconductor structures and devices comprising the epitaxial layer of MgxGe1?xO2?x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.
Type: Application
Filed: October 27, 2023
Publication date: February 22, 2024
Applicant: Silanna UV Technologies Pte Ltd
Inventor: Petar Atanackovic